About

I am a Staff Software Engineer in the Physical Design group at Actel Corporation. I hold a PhD in Electrical and Computer Engineering from the University of Waterloo.

My research interests include RTL synthesis (tech mapping, verification, logic optimization), VLSI placement, routing, and floorplanning, as well as graph drawing and facility layout. I'm also interested in heuristic methods to solve certain types of NP-hard problems (like graph partitioning, vertex ordering, and integer-linear programming), and approaches for solving certain difficult problems in SQL query optimization.

Publications

Journal Papers

  • Power minimization during FPGA placement, K. Vorwerk, A. Kennings, V. Pevzner, A. Kundu, M. Raman, J. Dunoyer, Y.-C. Hsu, To appear: IET Computer and Digital Techniques, 2009.
  • Improving Simulated Annealing-Based FPGA Placement with Directed Moves, K. Vorwerk, A. Kennings, J. Greene, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 28, Issue 2, pp. 179-192, February 2009.
  • VLSI Floorplan Repair Using Dynamic Whitespace Management, Constraint Graphs, and Linear Programming, K. Vorwerk, A. Kennings, M. F. Anjos, Journal of Engineering Optimization, Vol. 40 (6), pp. 559-577, 2008.
  • Force-directed methods for generic placement, A. Kennings, K. Vorwerk, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 10, pp. 2076-2087, October 2006.

Conference Papers

  • FPGA technology mapping with encoded libraries and staged priority cuts, A. Kennings, K. Vorwerk, V. Pevzner, A. Fox, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 143-150, Monterey, California, February 22-24, 2009.
  • A technique for minimizing power during FPGA placement, K. Vorwerk, M. Raman, J. Dunoyer, Y.-C. Hsu, A. Kundu, A. Kennings, IEEE International Conference on Field Programmable Logic and Applications, pp. 233-238, Heidelberg, Germany, September 8-10, 2008.
  • Improving annealing via directed moves, K. Vorwerk, A. Kennings, J. Greene, IEEE International Conference on Field Programmable Logic and Applications, pp. 363-370, Amsterdam, Netherlands, August 27-29, 2007. (winner outstanding paper award).
  • Improving timing-driven FPGA packing with physical information, D. T. L. Chen, K. Vorwerk, A. Kennings, IEEE International Conference on Field Programmable Logic and Applications, pp. 117-123, Amsterdam, Netherlands, August 27-29, 2007. (nominated outstanding paper award).
  • Floorplan repair using dynamic whitespace management, K. Vorwerk, A. Kennings, D. T. L. Chen, L. Behjat, Great Lakes Symposium on VLSI, pp. 552-557, Stresa-Lago Maggiore, Italy, March 11-13, 2007.
  • Mixed-size placement via line search, K. Vorwerk and A. Kennings, International Conference on Computer-Aided Design, pp. 899-904, San Jose, CA, USA, November 6-10, 2005.
  • An improved mulit-level framework for force-directed placement, K. Vorwerk and A. Kennings, Design Automation and Test in Europe, Volume 2, pp. 902-907, Munich, Germany, March 7-11, 2005.
  • Engineering details of a stable force-directed placer, K. Vorwerk, A. Kennings, A. Vannelli, International Conference on Computer-Aided Design, pp. 573-580, San Jose, CA, USA, November 7-11, 2004.
  • On Implicate Discovery and Query Optimization, K. Vorwerk, G. N. Paulley, IEEE International Database Engineering and Applications Symposium, pp. 2-11, 2002.

Patents

  • Glenn Paulley and Kristofer Vorwerk, Prime Implicates and Query Optimization in Relational Databases, U.S. 6665664 (2004).

Book Chapters

  • A. Kennings, K. Vorwerk, Force-directed and other continuous placement methods, in Handbook of algorithms for physical design automation, D. Mehta, C. Alpert, S. Sapatnekar, eds.; CRC Press, 2007.

Technical Reports

  • Robust minimum movement legalization via partitioning, constraint graphs and intelligent whitespace management, K. Vorwerk, A. Kennings, University of Waterloo, Department of Electrical and Computer Engineering, Technical Report: UW-ECE-#2006-08, 2006.
  • On the engineering of a stable analytic placer, A. Kennings, A. Vannelli, K. Vorwerk, University of Waterloo, Department of Electrical and Computer Engineering, Technical Report: UW-ECE-#2004-02, 2004.

Resume

Available upon request.